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2.1 Channel PWM Controller
DESCRIPTION
The WM8602 comprises a high performance stereo + sub PWM digital power amplifier controller. Simply by adding appropriate power output stages a 2.1 channel power amplifier may be built. Two identical full audio bandwidth channels, plus a reduced bandwidth sub channel are provided as PWM outputs. The PCM to PWM converter supports up to 2 channels of audio, in PCM input formats. The on board bass management enables the generation of a sub channel from the stereo PCM data. A Graphic Equaliser function is provided, plus selectable high frequency equalisation to suit different speaker types. Independent volume control for each channel is provided. The WM8602 PWM controller is compatible with integrated switching output stages available from a number of vendors or alternatively may be used with a discrete output stage configuration and achieve similar levels of performance. A Dynamic Peak Compressor with programmable attack and decay times is included, which allows headroom for tone control, bass management and extra digital gain to be provided, without clipping occurring. A Synchroniser allows slaving to LRCLK, thus making the WM8602 independent of source MCLK frequency and jitter. The device is controlled via a 2/3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is supplied in a 28-pin SSOP package. * *
WM8602
FEATURES
* * * * Multi-channel PWM audio amplifier controller Supports Stereo input Supports stereo or 2.1 with sub channel generation PWM Audio Performance with typical output stage - 100dB SNR (`A' weighted @ 48kHz) - 0.01% THD @ 1Watt - 0.1% THD @ 30Watt Integrated Bass Management support with adjustable filter Integrated 4-band Graphic Equaliser Adjustable output stage filter compensation for different speakers Volume control on each channel +24dB to -103.5dB in 0.5dB steps, with volume ramping and auto-mute functions Programmable Dynamic Peak Compressor avoids clipping even at high volume settings Internal PLL and optional crystal oscillator, supporting Audio and MPEG standards 2/3-Wire MPU Serial Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths De-emphasis support for stereo CMOS digital outputs
* * * *
* * * * *
APPLICATIONS
* * * * Hi-Fi systems Automotive Audio Boombox Active Speakers
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
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Copyright 2004 Wolfson Microelectronics plc
WM8602 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 ABSOLUTE MAXIMUM RATINGS.........................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY .....................................................................................................7 POWER CONSUMPTION ......................................................................................7 SIGNAL TIMING REQUIREMENTS .......................................................................8
POWER SUPPLY.......................................................................................................... 8 MASTER CLOCK TIMING ............................................................................................. 8 AUDIO INTERFACE TIMING - MASTER MODE .......................................................... 9
DEVICE DESCRIPTION.......................................................................................14
INTRODUCTION ......................................................................................................... 14 SIGNAL PATH............................................................................................................. 14 DIGITAL AUDIO INTERFACE ..................................................................................... 15 AUDIO INTERFACE CONTROL.................................................................................. 18 MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 19 SYNCHRONISER........................................................................................................ 22 CONTROL INTERFACE OPERATION ........................................................................ 23 INPUT PROCESSOR .................................................................................................. 24
BASS MANAGEMENT .........................................................................................25
GRAPHIC EQUALISER............................................................................................... 26 DIGITAL DEEMPHASIS .............................................................................................. 28 DIGITAL VOLUME CONTROL .................................................................................... 28 SOFT MUTE AND AUTO-MUTE ................................................................................. 29 DYNAMIC PEAK COMPRESSOR ............................................................................... 31 INTERPOLATION FILTERS ........................................................................................ 34 PCM TO PWM CONVERTER ..................................................................................... 35 STANDBY, OUTPUT DISABLE AND RESET MODES ................................................ 36 EXTERNAL POWER SUPPLY CLOCK ....................................................................... 37
REGISTER MAP...................................................................................................39
FILTER RESPONSES ................................................................................................. 40 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 41
APPLICATION NOTES ........................................................................................42
START-UP .................................................................................................................. 42 POWER SUPPLY CONNECTIONS............................................................................. 43
APPLICATIONS INFORMATION .........................................................................44
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 44 RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 44
PACKAGE DIMENSIONS ....................................................................................45 IMPORTANT NOTICE ..........................................................................................46
ADDRESS: .................................................................................................................. 46
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WM8602
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE WM8602SEDS/V WM8602SEDS/RV TEMPERATURE RANGE -25 to + 85C -25 to + 85C PACKAGE 28-pin SSOP (lead free) 28-pin SSOP (lead free, tape and reel) MOISTURE LEVEL SENSITIVITY MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260C 260C
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WM8602 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DVDD DIN LRCLK BCLK OPDIS MODE SCLK SDIN CSB EAPDB OPSWP BVDD AGND CLKPSU BGND BVDD OPRN OPRP BGND OPLN OPLP BVDD AVDD AGND XOP XIN DGND MCLK TYPE Supply Digital Input Digital Input/Output Digital IO Digital Input p.d. Digital Input p.d. Digital Input Digital Input/Output Digital Input Digital Output Digital Output Supply Supply Digital Output Supply Supply Digital Output Digital Output Supply Digital Output Digital Output Supply Analogue Supply Analogue Supply Digital Output Digital Input Supply Digital Input/Output Digital positive supply L/R channel data input Left/right word clock Audio interface bit clock Output disable 2/3 Wire control interface mode Serial interface clock Serial interface data Serial interface load signal External output stage power down PWM output positive Subwoofer channel PWM output buffer positive supply Analogue negative supply Clock for external PSU PWM output buffer ground supply PWM output buffer positive supply PWM output negative right channel PWM output positive right channel PWM output buffer ground supply PWM output negative left channel PWM output positive left channel PWM output buffer positive supply Analogue positive supply Analogue negative supply Crystal oscillator output connection DESCRIPTION
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Crystal oscillator input connection (may be left unconnected in slave mode) Digital negative supply Master clock; 256, 384, 512 fs (fs = word clock frequency) or 27MHz
Notes: Digital input pins have Schmitt trigger input buffers. Pins marked `p.u.' or `p.d.' have internal pull-up or pull down.
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WM8602
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Analogue supply voltage (AVDD) Digital supply voltage (DVDD) PWM output buffer supply voltage (BVDD) Voltage range inputs Master Clock Frequency Operating temperature range, TA Storage temperature Notes: 1. 2. GND power supplies (i.e. AGND, DGND, and BGND) must always be within 0.3V of each other. VDD power supplies (i.e. AVDD, DVDD, and BVDD) must always be within 0.3V of each other. MIN -0.3V -0.3V -0.3V DGND -0.3V 10MHz -20C -65C MAX +5V +5V +5V DVDD +0.3V 50MHz +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Analogue supply range Digital supply range PWM output buffer supply Ground SYMBOL AVDD DVDD BVDD AGND, DGND, BGND TEST CONDITIONS MIN 2.7 2.7 2.7 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
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WM8602 ELECTRICAL CHARACTERISTICS
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Test Conditions AVDD, BVDD, DVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, TA = -20 to +85oC, fs = 44.1kHz/48kHz, MCLK = 256fs unless stated. PARAMETER Input capacitance Input leakage Oscillator Input XIN LOW level Input XIN HIGH level Input XIN capacitance Input XIN leakage Output XOP LOW Output XOP HIGH Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Pull-up/pull-down resistance Output LOW Output HIGH Digital Logic Levels (LVDS Levels) Output differential voltage Offset voltage Termination load PCM to PWM converter Digital SNR Typical SNR with output stage (A-weighted) Typical Dynamic Range with output stage Digital THD+N at 0dBfs Typical THD+N at 30Watt with output stage Typical THD+N at 1Watt with typical output stage Typical IMD (CCIF - 19/20kHz) Typical IMD (SMPTE - 60Hz/7kHz) PCM to PWM converter Digital SNR Typical SNR with output stage (A-weighted) Typical Dynamic Range with output stage Digital THD+N at 0dBfs Typical THD+N at 30Watt with output stage Typical THD+N at 1Watt with typical output stage Typical IMD (CCIF - 19/20kHz) Typical IMD (SMPTE - 60Hz/7kHz) Subwoofer5 Subwoofer
5
SYMBOL Ci Ileak VXIL VXIH CXI IXleak VXOL VXOH VIL VIH VOL VOH VOD VOS RT
TEST CONDITIONS
MIN
TYP 3 0.1
MAX 4 0.5 0.44 AVDD
UNIT pF A V V pF mA V V V V k V V
0 0.77 4 0.10 15pF load capacitors 15pF load capacitors 0.1 1.2 0.11 0.4 1.3
5 0.13 0.5 1.4 0.3 x DVDD
0.7 x DVDD 100 IOL=+1mA IOL=-1mA RT=100 RT=100 20pF load L, R L, R L, R L, R L, R L, R L, R L, R 0.9 x DVDD 200 0.95 350 1.25 100 105 100 100 0.001 0.1 0.01 -70 -70 500 1.4 200 400 0.1 x DVDD
mV V dB dB dB % % % dBFS dBFS
105 100 100 0.001 0.1 0.01 -70 -70
Subwoofer5 Subwoofer5 Subwoofer5 Subwoofer5 Subwoofer5 Subwoofer5
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WM8602
Test Conditions AVDD, BVDD, DVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, TA = -20 to +85oC, fs = 44.1kHz/48kHz, MCLK = 256fs unless stated. PARAMETER PWM buffer drive strength PWM pulse repetition rate Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz AES17 low pass filter, except where noted an A-weight filter is used. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. The XIN input supports both a clock as well as a crystal input. Parameter guaranteed by design. Validated using the following filter PARAMETER Filter Stopband Note: A third order differential RC filter has been used -3dB 1.00 kHz SYMBOL TEST CONDITIONS MIN TYP MAX UNIT SYMBOL Isource Isink fPWM TEST CONDITIONS CMOS 20pF load fs = 44.1kHz fs = 48kHz MIN 25
4
TYP
MAX
UNIT mA mA
254 352.8 384
kHz kHz
3. 4. 5.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the RMS values, of (Noise + Distortion)/Signal.
3.
POWER CONSUMPTION
MODE DESCRIPTION TYPICAL SUPPLY CURRENTS [mA] IAVDD AVDD, DVDD, BVDD = 3.3V OFF Standby Mute Stereo 2.1 Table 1 Supply Current Consumption 0 0.02 1.76 1.76 0 0.28 27.2 27.7 0 0 7.55 7.55 0 0.30 36.5 37.0 0 0.99 121 122 IDVDD IBVDD TOTAL CURRENT [mA] TOTAL POWER [mW]
Notes: 1. 2. TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 27 kHz, 24-bit data All figures are kHz 1kHz input sine wave @ 0dB.
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WM8602 SIGNAL TIMING REQUIREMENTS
POWER SUPPLY
Test Conditions AGND, DGND, BGDN = 0V, TA = +25C PARAMETER Power Supply Timing Information AVDD: rise time 10% to 90% AVDD DVDD: rise time 10% to 90% DVDD BVDD: rise time 10% to 90% BVDD Table 2 Power Supply Timing Requirements tAR tDR tBR 0.2 0.2 0.2 50 50 50 SYMBOL MIN TYP MAX
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UNIT ms ms ms
MASTER CLOCK TIMING
XTI/MCLK
tMCLKY
Figure 1 Master Clock Timing Requirements Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25C PARAMETER System Clock Timing Information XTI/MCLK System clock cycle time XTI/MCLK Duty cycle XTI/MCLK Period Jitter XTI/MCLK Rise/Fall times 10% to 90% AVDD Table 3 Master Clock Timing Requirements tMCLKY 20 40:60 100 60:40 200 3 ns % ps ns SYMBOL MIN TYP MAX UNIT
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WM8602
AUDIO INTERFACE TIMING - MASTER MODE
BCLK (Output) t LRCLK (Output) t DIN
DST DL
t
DHT
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge DIN setup time to BCLK rising edge DIN hold time from BCLK rising edge Table 4 Audio Interface Timing - Master Mode tDL tDST tDHT 10 10 10 ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8602
AUDIO INTERFACE TIMING - SLAVE MODE
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Figure 3 Digital Audio Data Timing - Slave Mode
Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low BCLK rise/fall times LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge LRCLK rise/fall times DIN hold time from BCLK rising edge Table 5 Audio Interface Timing - Slave Mode Note: BCLK period should always be greater than or equal to MCLK period. tDH 10 tLRSU tLRH 10 10 5 tBCY tBCH tBCL 50 20 20 5 ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8602
CONTROL INTERFACE TIMING - 3-WIRE MODE
tCSL CSB tSCY tSCH SCLK tSCL tSCS
tCSH
tCSS
SDIN tDSU tDHO
LSB
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode
Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed Table 6 Control Interface Timing - 3-Wire Serial Control Mode tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 60 80 30 30 20 20 20 20 20 2 8 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8602
CONTROL INTERFACE TIMING - 2-WIRE MODE
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t3 SDIN
t5 t4 t6 t2 t7 t10
t3
t8
SCLK t1
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed Table 7 Control Interface Timing - 2-Wire Serial Control Mode t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 2 600 900 8 600 1.3 600 600 100 300 300 400 kHz ns us ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8602
PWM OUTPUT TIMING
tPWMH OPXXX tPWMCY
tPWML
Figure 6 PWM Output Timing
Test Conditions AVDD, DVDD, BVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, TA = -20 to +85 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information PWM Frequency PWM Low Pulse-Width PWM High Pulse-Width CMOS Mode PWM Rise Time1 PWM Fall Time1 Table 8 PWM Interface Timing Note: 1. Parameter guaranteed by design 20pF load 20pF load 1.5 1.5 2.3 2.3 ns ns tPWMCY tPWML tPWMH 122 122 384 kHz ns ns SYMBOL/NOTE MIN TYP MAX UNIT
o
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WM8602 DEVICE DESCRIPTION
INTRODUCTION
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The WM8602 is a high-performance multi-channel Pulse-Width Modulation (PWM) digital power amplifier controller. The device accepts up to 2 channels of audio in PCM input format, and outputs 2 PWM full-bandwidth channels, plus a PWM sub-woofer channel. The outputs are suitable for directly driving integrated switching output stages available from a number of vendors. The device is also compatible with discrete MOSFET output stages. In both cases, Wolfson Microelectronics offer Reference Designs for complete PWM digital power amplifiers. The WM8602 has a configurable input processor which accepts Stereo channels of PCM audio and outputs Stereo or 2.1 outputs. The sub channel is generated from the filtered sum of the low frequency components of the input data. The device has a Bass Management function, which has low-pass and high-pass filters for feeding the sub channel and main output channels. It also provides selectable boost for the LFE channel. Each channel can be configured to drive either "large" full-range speakers or "small" satellite speakers with limited bass capability. A Tone Control function is provided, plus selectable high frequency equalisation to compensate for different loudspeaker characteristics. Independent volume control is provided for all channels, with comprehensive mute features. A Dynamic Peak Compressor with programmable attack and decay times is included, which allows headroom for tone control, bass management and extra digital gain to be provided, without clipping occurring. The device is controlled via a 2/3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mute, de-emphasis and power management facilities.
SIGNAL PATH
The WM8602 receives digital input data via a 2-channel digital audio interface. The data is processed in turn by the Input Processor, Bass Management and Equalisation, Volume Control and Dynamic Peak Compressors, Interpolation Filters, and PCM-PWM Converters, as shown in Figure 7. The PWM signals are output via CMOS drivers.
2 Channel Input
Input Processor
Bass Management and Equalisation
Volume Control / Dynamic Peak Compressors
Interpolation Filters
PCM - PWM Converter
CMOS Output
Figure 7 Signal Processing Block Diagram
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Product Preview Parameter L / R channel SUB channel Table 9 Signal Path Group Delay Group Delay 47 22 Unit samples samples fs=48kHz 1.0 0.5
WM8602
Unit ms ms
Note: The shorter delay on the SUB channel will not significantly affect audio performance. (It is equivalent to moving the subwoofer forwards by about 15cm.)
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting audio data into the WM8602. It uses five pins: * * * DIN: L+R channel data input LRCLK: Data alignment clock BCLK: Bit clock, for synchronisation
The clock signals BCLK and LRCLK can be outputs when the WM8602 operates as a master, or inputs when it is a slave (see Master and Salve Mode Operation, below).
MASTER AND SLAVE MODE OPERATION
The WM8602 can be configured as either a master or slave mode device. As a master device the WM8602 generates BCLK and LRCLK and thus controls sequencing of the data transfer on the data channels. In slave mode, the WM8602 receives data and clock signals over the digital audio interface. The mode can be selected by writing to the MS bit (see Table 23). Master and slave modes are illustrated below.
Master Mode Figure 8 Operation Mode
Slave Mode
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK Audio data is applied to the internal filters via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP mode A DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits. Except that 32 bit data is not supported in right justified mode. DIN and LRCLK are sampled on the rising, or falling edge of BCLK. In left justified, right justified and I2S modes the digital audio interface receives data on the DIN input. Audio Data for each stereo channel is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per DACLRC period is 2 times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met.
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WM8602
Product Preview In DSP mode A or B, all channels are time multiplexed onto DIN. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is 8 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned (see Figure 9, Figure 10 and Figure 11).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right samples.
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition. LRCLK is high during the left samples and low during the right samples.
Figure 10 Right Justified Mode Timing Diagram
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WM8602
I S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left samples and high during the right samples.
2
Figure 11 I2S Mode Timing Diagram
DSP MODE A AND B
In DSP mode, the Left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
st nd
Figure 12 DSP Mode A Timing Diagram
Figure 13 DSP Mode B Timing Diagram
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WM8602
No BCLK edges are allowed between the data words. MODE Stereo L, R INPUT FORMAT (ORDER)
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SUPPORTED MODES No restrictions apply
Table 10 DSP Mode Input Format
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master/slave mode are summarised below. MS selects audio interface operation in master or slave mode. In Master mode BCLK and LRCLK are outputs and the frequency of LRCLK is set by the sample rate control bits SR[3:0]. In Slave mode BCLK and LRCLK are inputs (refer to Table 12 for sample rate control in this case). REGISTER ADDRESS R2 (02h) Audio IF Format BIT 8 LABEL BCLKINV DEFAULT 0 DESCRIPTION BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Left/Right channel swap 1 = swap left and right data in audio interface 0 = output left and right data as normal Right, left and I2S modes - LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity (as show in e.g. Figure 12) DSP Mode - A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = DSP Mode 10 = I2S Format 01 = Left justified 00 = Right justified
7
MS
0
6
LRSWAP
0
4
LRP
0
3:2
WL[1:0]
10
Table 11 Audio Data Format Control Notes: 1. Right Justified mode does not support 32-bit data.
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WM8602
MASTER CLOCK AND AUDIO SAMPLE RATES
The WM8602 supports a wide range of master clock frequencies on the MCLK pin, and can generate many commonly used audio sample rates directly from the master clock. (See Table 14 for details.) REGISTER ADDRESS R0 (00h) Clocking 0 BIT LABEL CMAST 1 DEFAULT DESCRIPTION Master Clock Mode 0 = MCLK input 1 = XIN input MPEG Mode 0 = see Table 14 1 = MCLK is 27MHz Master Clock Active Edge 0 = positive edge 1 = negative edge Master Clock Divide by 2 1 = MCLK is divided by 2 0 = MCLK is not divided
1
MPEG
1
2
MEDGE
0
3
CLKDIV2
0
Table 12 Clocking and Sample Rate Control (1) If the WM8602 is running in MPEG mode (i.e. fXIN = 27MHz) the sample can be detected automatically if the SRDET bit is set. In this case, the SR bits do not need programming.
REGISTER ADDRESS R1 (01h) Sample Rate
BIT 3:0 4
LABEL SR [3:0] SRDET
DEFAULT 0000 1
DESCRIPTION Sample Rate Control. Refer to Table 14. Sample rate detect 1 = Enabled (in MPEG mode only) 0 = Disabled
Table 13 Clocking and Sample Rate Control (2) The clocking of the WM8602 is controlled using the CLKDIV2 and SR control bits. Setting the CLKDIV2 bit divides MCLK by two internally. Each value of SR[3:0] selects one combination of MCLK division ratios and hence one combination of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK changes the sample rates change proportionally.
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WM8602
MCLK / XIN CLKDIV2=0 [MHz] 12.288 24.576 11.2896 22.5792 18.432 36.864 16.9344 33.8688 CLKDIV2=1 [MHz] 24.576 49.152 22.5792 45.1584 36.864 not supported 33.8688 not supported [kHz] 32 48 96 192 44.1 88.2 176.4 32 48 96 192 44.1 88.2 176.4 27.000 not supported (MPEG = 1) 32 44.1 48 88.2 96 176.4 192 Table 14 Master Clock and Sample Rates (MCLK/384) (MCLK/256) (MCLK/256) (MCLK/128) (MCLK/256) (MCLK/256) (MCLK/128) (MCLK/512) (MCLK/384) (MCLK/384) (MCLK/192) (MCLK/384) (MCLK/384) (MCLK/192) 0001 0000 0011 0010 0100 0111 0110 1001 1000 1011 1010 1100 1111 1110 0001 0100 0000 0111 0011 0110 0010 AUDIO SAMPLE RATE (MPEG = 0) SR [3:0]
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The following Figure 14, Figure 15, Figure 16 and Figure 17 illustrate the different Clocking and Audio IF modes.
Figure 14 Clock and Audio IF: Clock Master / Audio IF Slave (Default)
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WM8602
Figure 15 Clock and Audio IF: Clock Master / Audio IF Master
Figure 16 Clock and Audio IF: Clock Slave / Audio IF Slave
Figure 17 Clock and Audio IF: Clock Slave / Audio IF Master
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WM8602
SYNCHRONISER
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The WM8602 contains a synchroniser circuit to support the synchronisation of an external LRCLK to the local LRCLK. This mode is only supported in MPEG mode. The specification of the synchroniser circuit is:
Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, fXIN = 27MHz, Slave Mode, fs = 48kHz, 24-bit data, unless otherwise stated. PARAMETER Lock time LRCLK frequency offset LRCLK drift in Lock SYMBOL tlock foffLRCLK driftLRCLK MIN TYP <1 1000 MAX 2 10'000 0.2 6 Table 15 Synchroniser Specification REGISTER ADDRESS R32 (20h) Synchroniser (1) BIT 0 LABEL SYNCEN DEFAULT 1 DESCRIPTION Synchroniser Enable 0: Disable 1: Enable (in MPEG mode only) Minimum Synchroniser Gain 00: minimum gain = 20 01: minimum gain = 21 2 10: minimum gain = 2 11: minimum gain = 23 Maximum Synchroniser Gain 8 00: maximum gain = 2 01: maximum gain = 210 10: maximum gain = 212 14 11: maximum gain = 2 Hold Synchroniser (and SR detect) 1 : Synchroniser in hold mode UNIT s ppm fs ppm/s Hz
2:1
GMIN[1:0]
10
4:3
GMAX[1:0]
10
5 Table 16 Synchroniser (1)
HOLD
0
REGISTER ADDRESS R33 (21h) Synchroniser (2)
BIT 2:0
LABEL SYNTO[2:0]
DEFAULT 100
DESCRIPTION Synchroniser Gain time-out 000: 0.2 ms 001: 0.5 ms 010: 1 ms 011: 2 ms 100: 5 ms (default) 101: 10 ms 110: 20 ms 111: 50 ms
Table 17 Synchroniser (2)
The next table illustrates recommendation for the Synchroniser loop gain G (see also Table 16) and time-out time (Table 17) with respect to the LRCLK frequency and the resulting Synchroniser lock time.
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WM8602
FOFFLRCLK [ppm] 100 1000 10'000 G max 28 2 2
10 10
min 20 20 2
0
GAIN TIME-OUT [ms] ~1 ~4 ~20
Table 18 Synchroniser Setup and Locking Note: The Synchroniser requires a continuously running LRCLK. If that is not the case the HOLD signal has to be applied to avoid the synchronizer drifting.
CONTROL INTERFACE OPERATION
SELECTION OF CONTROL MODE
The WM8602 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin selects the interface format. An internal pull-down resistor configures the Control Interface to a default 2 wire format. MODE Low High INTERFACE FORMAT 2 wire (default) 3 wire
Table 19 Control Interface Mode Selection The WM8606 Control Interface operates as a slave device only.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8602 is controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire interface protocol is shown in Figure 13.
CSB SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 18 3-wire Serial Interface The bits B[15:9] are Control Address Bits and the bits B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8602 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8602). The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8602 and the R/W bit is `0', indicating a write, then the WM8602 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1', the WM8602 returns to the idle condition and wait for a new start condition and valid address.
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Product Preview Once the WM8602 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8602 register address plus the first bit of register data). The WM8602 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8602 acknowledges again by pulling SDIN low. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8602 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
DEVICE ADDRESS RD / WR (7 BITS) BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 7 TO 0)
ACK (LOW)
SCLK
START
register address and 1st register data bit
remaining 8 bits of register data
STOP
Figure 18 2-Wire Serial Control Interface The WM8602 has two possible device addresses, which can be selected using the CSB pin. CSB STATE Low High DEVICE ADDRESS 0011010 0011011
Table 20 2-Wire MPU Interface Address Selection
INPUT PROCESSOR
The WM8602 supports the production of stereo or 2.1 outputs from stereo inputs according to Table 21. OUTPUT CONFIGURATIONS CONFIG Stereo 2.1 FL OUT FR OUT SUB OUT
* *
* *
*
Table 21 Output Configuration
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WM8602
REGISTER ADDRESS R3 (03h) Input/Output Configuration BIT 3 LABEL OPCFG[1:0] DEFAULT 1 DESCRIPTION Output Configuration 0 = Stereo 1 = 2.1
Table 22 Input and Output Configuration Register The WM8602 also supports Stereo input - Stereo output via the Bass Management filtering options, as discussed in Bass Management (page 25). In this case, the output configuration is set to 2.1. Where there are a different number of input and output channels, the data is processed as follows. Refer to the section on Bass Management (page 25) for details on how the sub-channel is created.
STEREO INPUT - STEREO OUTPUT
The Left and Right inputs are passed to the Left and Right Outputs. All other channels are muted.
STEREO INPUT - 2.1 OUTPUT
The Left and Right inputs are passed to the Left and Right outputs. The low-frequency contents of the Left and Right inputs, may be optionally mixed and passed to the SUB output.
BASS MANAGEMENT
The Bass-Management function filters and combines the input signals to produce a low-pass filtered output for the sub-woofer channel and high-pass filtered outputs for the remaining channels. The filters have selectable cut-off frequencies to match different types of sub-woofer and satellite speakers. The filters are designed so that the cut-off frequencies for the high-pass and low-pass filters remain constant irrespective of the sampling frequency used. 1st order filters are used for the low-pass and high-pass filters.
Figure 19 Bass Management The high-pass filters pairs can be bypassed to allow full-range speakers to be used on the main output pair. The Bass-Management also provides a selectable LFE boost of 10dB via the LFEBOOST control bit. Additional gain-adjust is provided after this block (refer to Digital Volume Control, page 28).
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REGISTER ADDRESS R13 (0Dh) Bass Management Filter BIT 1:0 LABEL LPHPCO[1:0] DEFAULT 01
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DESCRIPTION Low-/High-Pass Cutoff Frequency (-3dB) 00 = 75Hz 01 = 100Hz 10 = 133Hz 11 = 178Hz LFE Boost Enable 0 = Boost Disabled 1 = 10dB Boost Enabled
2
LFEBOOST
0
Table 23 Bass Management Filter REGISTER ADDRESS R14 (0Eh) Bass Management Filter Bypass BIT 0 LABEL HPENF DEFAULT 1 DESCRIPTION Left/Right High-Pass Filter 0 = High-Pass Filter bypassed 1 = High-Pass Filter enabled Left/Right Low-Pass Filter Enable 0 = Low-Pass Filter output disabled 1 = Low-Pass Filter output enabled
3
LPENF
1
Table 24 Bass Management Filter Bypass
GRAPHIC EQUALISER
The WM8602 has a 4-band Graphic Equaliser on the main channels. The three upper bands are controlled via registers (see Table 25, Table 26, Table 27 and Table 28). The lowest band is controlled via the subwoofer volume control (see VOLS in Table 31). The function has selectable cutoff frequencies which are independent of sample rate. The boost/cut for the upper three bands is controllable in 1.5dB steps from -6dB to +9dB via the EQB control bits. REGISTER ADDRESS R15 (0Fh) EQ Band 1 Gain Control BIT 3:0 LABEL EQ1GF [3:0] DEFAULT 1111 (Disabled) DESCRIPTION Band 1 Left/Right Gain 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable
Table 25 EQ Band 1 Gain Control REGISTER ADDRESS R16 (10h) EQ Band 2 Gain Control BIT 3:0 LABEL EQ2GF [3:0] DEFAULT 1111 (Disabled) DESCRIPTION Band 2 Left/Right Gain 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable
Table 26 EQ Band 2 Gain Control
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WM8602
REGISTER ADDRESS R17 (11h) EQ Band 3 Gain Control BIT 3:0 LABEL EQ3GF [3:0] DEFAULT 1111 (Disabled) DESCRIPTION Band 3 Left/Right Gain 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable
Table 27 EQ Band 3 Gain Control
REGISTER ADDRESS R18 (12h) EQ CentreFrequency Control
BIT 0
LABEL EQ1CF
DEFAULT 1
DESCRIPTION Band 1 Left/Right Centre-Frequency 0 = High Cutoff (500Hz) 1 = Low Cutoff (250Hz) Band 2 Left/Right Centre-Frequency 0 = High Cutoff (2kHz) 1 = Low Cutoff (1kHz) Band 3 Left/Right Cutoff Frequency 0 = High Cutoff (8kHz) 1 = Low Cutoff (4kHz)
2
EQ2CF
1
4
EQ3CF
1
Table 28 EQ Frequency Control Band 0 is controlled via the sub-woofer volume control register R11 as described in Table 31. The functionality to add/subtract the boost/cut setting to the sub-woofer volume must be written into the software controller for the chip. The Band 0 Cutoff frequency can be changed using the corner frequency of the low-pass/high-pass filters as described in Table 23.
DIGITAL LOUDSPEAKER EQUALISER
A loudspeaker equaliser is provided to compensate for high-frequency variations that can occur when loudspeakers of different impedances are used with different output filters in typical output stages. The equaliser has selectable cut-off frequencies which are independent of sample rate. The gain at 20kHz is controllable in 0.5dB steps from -1.5dB to +2dB via the LSEQ control bit. The settings are applied to Left and Right channels simultaneously. REGISTER ADDRESS R19 (13h) Loudspeaker Equaliser BIT 0 LABEL LSCO DEFAULT 0 DESCRIPTION LSEQ Filter Characteristic 0 = High Cutoff (15kHz) 1 = Low Cutoff (10kHz) High Frequency Equalisation 000 = +2dB 001 = +1.5dB 010 = +1dB 011 = +0.5dB 100 = Disable 101 = -0.5dB 110 = -1dB 111 = -1.5dB
3:1
LSEQ [2:0]
100 (Disabled)
Table 29 Loudspeaker Equaliser
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DIGITAL DEEMPHASIS
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The digital `de-emphasis' is used to equalize pre-emphasised digital CD recordings. De-emphasis filtering is available on the Left and Right channels only, for sample rates of 32kHz, 44.1kHz and 48kHz. The settings are applied to the two channels simultaneously. REGISTER ADDRESS R20 (14h) De-emphasis BIT 0 LABEL DEEMP DEFAULT 0 DESCRIPTION De-emphasis Control 0 = No De-emphasis 1 = De-emphasis enabled
Table 30 De-emphasis Refer to Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35 for details of the DeEmphasis modes at different sample rates. Note: Using the De-emphasis filters for other sample rates as defined above will result in a frequency response error as shown in Figure 31, Figure 33 and Figure 35.
DIGITAL VOLUME CONTROL
The volume control allows the gain of each channel to be independently adjusted in 0.5dB steps from -103.5dB to +24dB. When the Dynamic Peak Compressor (see below) is enabled, gains of greater than 0dB can be applied without digital clipping occurring. The volume control has a digital zero-cross circuit which minimises clicks during changing the volume. An update control bit is provided which allows the volume setting on each channel to be first stored in an intermediate latch, then afterwards applied simultaneously to all channels. If UPDATE=0, the Volume value will be written to the pre-latch but not applied to the relevant channel. If UPDATE=1, all pre-latched values will be applied from the next input sample. The value of UPDATE itself is not latched. To prevent audible clicks, the volume control includes a ramp function which automatically ramps the volume in small steps between register updates. The ramp rate is 256dB/s 5%. REGISTER ADDRESS R4 (04h) Left Volume BIT 7:0 8 LABEL VOLL[7:0] UPDATE DEFAULT 10110001 (-15dB) 0 DESCRIPTION Left Volume in 0.5dB steps. Refer to Table 14 Volume Update 0 = Store LVOL in intermediate latch (no gain change) 1 = Store and Update all channel gains Right Volume in 0.5dB steps. Refer to Table 14 Volume Update 0 = Store RVOL in intermediate latch (no gain change) 1 = Store and Update all channel gains Sub Volume in 0.5dB steps. Refer to Table 14 UPDATE 0 = Store SVOL in intermediate latch (no gain change) 1 = Store and Update all channel gains
R5 (05h) Right Volume
7:0 8
VOLR [7:0] UPDATE
10110001 (-15dB) 0
R10 (0Ah) Subwoofer Volume
7:0 8
VOLS [7:0] UPDATE
10110001 (-15dB) 0
Table 31 Volume Control
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WM8602
VOLXX[7:0] 00(hex) 01(hex) : : CF(hex) : : FE(hex) FF(hex) Table 32 Volume Control Levels VOLUME LEVEL -dB (mute) -103dB : : 0dB : : +23.5dB +24dB
DUAL VOLUME CONTROL
Setting the DVC register bit causes the volume settings to be applied in pairs. For example, the DVCF causes the Left channel volume settings to be applied to both the Left and Right channels from the next audio input sample. No update to the VOL registers is required for DVC to take effect. REGISTER ADDRESS R11 (0Bh) Dual Volume Control BIT 0 LABEL DVCF DEFAULT 0 DESCRIPTION Dual Volume Control - Left/Right Channels: 0 : Use VOLFR setting for Right channel 1: Apply VOLFL setting to Right channel
Table 33 Dual Volume Control
SOFT MUTE AND AUTO-MUTE
The WM8602 has a Soft Mute function set by the SMUTE control bit. Figure 20 shows the application and release of SMUTE while a full amplitude sinusoid is being played at 48kHz sampling rate. When SMUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards zero with a time constant of approximately 64 input samples. When SMUTE is turned off, the output will restart almost immediately from the current input sample, thus possibly causing a pop sound. This function is disabled by default.
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1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005
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0.006
Figure 20 Application and Release of Soft Mute An auto-mute function is provided which automatically mutes the output stage when a digital silence period is detected. Digital silence is defined as a consecutive period of 1024 zero input samples at the output of the volume control. Auto-mute will be removed as soon as the volume control output becomes non-zero. (Please note that on the sub channel the noise level is greatly reduced, rather than complete digital silence.) To achieve digital silence, you can do one of the following: * * * Turn on auto-mute and set the volume control to zero. Turn on auto-mute and input zero data on the serial data input pins with the bass management filters disabled. (Page 25) Turn on auto-mute and soft mute.
The auto-mute operates independently for Left/Right and Subwoofer channels and can be enabled or disabled separately. The mute features maximize the SNR of the PWM amplifier system. Soft-mute will only maximize the SNR for Left/Right or Subwoofer channels if enabled. REGISTER ADDRESS R12 (0Ch) Mute BIT 0 LABEL SMUTE DEFAULT 0 DESCRIPTION Digital Soft Mute 0 = disable (signal active) 1= enable Left/Right Auto-mute 0 = disable 1 = enable Subwoofer Auto-mute 0 = disable 1 = enable
1
AMUTEF
1
4
AMUTESB
1
Table 34 Mute
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WM8602
DYNAMIC PEAK COMPRESSOR
The WM8602 includes a Dynamic Peak Compressor for each channel, which prevents the occurrence of digital clipping when gains in excess of 0dB are applied. The compressor automatically adjusts the signal amplitude to allow headroom for the LFE boost, sub-woofer mixing, tone controls, loudspeaker equalisation and digital volume control. The compressor has a programmable limit threshold, programmable attack and decay time-constants, a frequency-dependent decay mode, and built-in zero-cross detect. The compressor can be configured either to operate independently on all channels (DUAL MONO), or on linked channel-pairs (STEREO).
COMPRESSOR THRESHOLD
The compressor has a digital peak detector which tracks the maximum input signal level at the output of the volume control. With reference to Figure 21, if this signal is below the threshold set by control bit THRESH, the compressor operates transparently with no change to the signal level. However, if peak signal rises above the threshold, the gain through the compressor is modified so that the upper part of the curve is followed. This ensures that the output signal does not exceed 0dB.
ATTACK AND DECAY TIMES
The attack time-constant ATK controls how fast the gain is reduced when the signal goes above the threshold. It is defined as the time taken for the gain to reduce by 6dB. Normally a short attack timeconstant is used to prevent the signal clipping when a high-amplitude transient occurs. The decay time-constant DCY controls how fast the gain is increased when the signal begins to fall again. It is defined as the time taken for the gain to increase by 6dB. Normally, the decay timeconstant is much longer than the attack time-constant, to prevent the input signal from entering repeated limiting cycles. The frequency-dependent decay feature automatically detects the input frequency and sets the decay time to decay slower for low frequency signals. This reduces low-frequency signal distortion by preserving the waveform of each input cycle, whilst allowing the compressor to respond quickly to high frequency transients. This feature is enabled via the FDEP control bit.
Output Level (dB)
0dB
THRESH [dB]
-12
-18
+12dB +6dB 0dB -6dB
-24
-12dB typical Volume Control Setting
-30
-36 -36 -30 -24 -18 -12 -6 0 +6 +12
Peak Input Level [dB]
Figure 21 Dynamic Peak Compressor Characteristics
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REGISTER ADDRESS R21 (15h) Left/Right Channels Dynamic Peak Compressor
BIT 0
LABEL PLENF
DEFAULT 1
DESCRIPTION Left/Right Channel Compressor Enable 0 = disable 1 = enable
Table 35 Left/Right Channel Dynamic Peak Compressor (1)
REGISTER ADDRESS R22 (16h) Left/Right Channels Dynamic Peak Compressor
BIT 2:0
LABEL ATK[2:0]
DEFAULT 010
DESCRIPTION Left/Right Channel Attack Rate 000 = 170s 001 = 330s 010 = 670s 011 = 1.33ms 100 = 2.67ms 101 = 5.33ms 110 = 10.7ms 111 = 20.1ms Left/Right Channel Decay Rate 000 = 340ms 001 = 680ms 010 = 1.36s 011 = 2.73s 100 = 5,46s 101, 110, 111 = 10.9s Left/Right Channel Compressor Thresholds 00 = -12dB 01 = -9dB 10 = -6dB 11 = -3dB Frequency-dependent decay 0 = disable 1 = enable
5:3
DCY[2:0]
011
7:6
THRESH[1:0]
11
8
FDEP
0
Table 36 Left/Right Channel Dynamic Peak Compressor (2)
REGISTER ADDRESS R23 (17h) Sub Channel Dynamic Peak Compressor
BIT 0
LABEL PLENSUB
DEFAULT 1
DESCRIPTION Sub Channel Compressor Enable 0 = disable 1 = enable
Table 37 Subwoofer Channel Dynamic Peak Compressor (1)
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WM8602
REGISTER ADDRESS R24 (18h) Sub Channel Dynamic Peak Compressor BIT 2:0 LABEL ATK[2:0] DEFAULT 010 DESCRIPTION Sub Channel Attack Rate 000 = 170s 001 = 330s 010 = 670s 011 = 1.33ms 100 = 2.67ms 101 = 5.33ms 110 = 10.7ms 111 = 20.1ms Sub Channel Decay Rate 000 = 340ms 001 = 680ms 010 = 1.36s 011 = 2.73s 100 = 5,46s 101, 110, 111 = 10.9s Sub Channel Compressor Thresholds 00 = -12dB 01 = -9dB 10 = -6dB 11 = -3dB Frequency-dependent decay 0 = disable 1 = enable
5:3
DCY[2:0]
011
7:6
THRESH[1:0]
11
8
FDEP
0
Table 38 Subwoofer Channel Dynamic Peak Compressor (2)
ZERO-CROSS DETECT
The Dynamic Peak Compressor has a zero-cross detect which minimises clicks during gain changes. The zero-cross detect can be enabled/disabled for Left/Right or Subwoofer channels. The zero-cross has a timeout feature which ensures that the volume will change even if the input has a large DC offset. Once a new gain has been requested from the Dynamic Peak Compressor, the zero-cross detector will wait for a zero-cross for 25 to 50 ms before applying the gain change. REGISTER ADDRESS R25 (19h) Volume Control ZeroCross BIT 0 LABEL ZCF DEFAULT 1 DESCRIPTION Zero-Cross Enable - Left/Right Channels: 0 : Disable Zero-Cross 1: Enable Zero-Cross Zero-Cross Enable - Sub Channel: 0 : Disable Zero-Cross 1: Enable Zero-Cross Zero Cross Timeout Enable: 0 : Disable Zero-Cross Timeout 1: Enable Zero-Cross Timeout
3
ZCSUB
1
4
ZCT
1
Table 39 Volume Control Zero-Cross
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INTERPOLATION FILTERS
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The WM8602 uses two types of interpolation filters, selected according to sampling frequency, as shown in Table 39. SAMPLING FREQUENCY 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz Table 40 Interpolation Filter Types FILTER TYPE Main Channels 0 0 0 0 0 1 1 INTERPOLATION Main Channels 12x 8x 8x 4x 4x 2x 2x SUB 6x 4x 4x 2x 2x 1x 1x
FILTER TYPE 0
PARAMETER Filter Passband Stopband Passband ripple Stopband Attenuation Group Delay Table 41 Digital Filter 0 Characteristics f > 0.546fs -60 23 0.05 dB -3dB 0.484 0.05 0.454 fs fs dB dB samples SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
FILTER TYPE 1
PARAMETER Filter Passband Stopband Passband ripple Stopband Attenuation Group Delay Table 42 Digital Filter 1 Characteristics The subwoofer filter characteristic is defined in table -60 6 0.723 0.05 0.242 fs fs dB dB samples SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
FILTER TYPE SUBWOOFER
PARAMETER Sample Rate 32k 44k1 48k 88k2 96k 176k 192k Table 43 Subwoofer Filter Characteristic Note: * indicates no interpolation filters 2.0 2.7 3.0 6.1 6.8 * * 10.7 14.5 15.8 32.1 34.9 * * kHz kHz kHz kHz kHz kHz kHz SYMBOL TEST CONDITIONS -0.1dB -3dB UNIT
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WM8602
The PCM to PWM converter converters the Pulse-Code Modulated (PCM) signal into a highly linear Pulse-Width Modulated (PWM) signal. Table 44 defines the Pulse Repetition Frequency, (PRF), output clock rate (OBCLK) and minimum pulse width for each supported sampling frequency.
PCM TO PWM CONVERTER
tOBCLK tPWMP
tPWMM tPWMP
tPWMM
Figure 22 PCM to PWM Converter
The PRF Frequency (TPWMP) of the Sub-woofer channel is half of the frequency defined in Table 44 in order to reduce power dissipation in the output stage. SAMPLING FREQUENCY [kHz] 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz 384 352.8 384 352.8 384 352.8 384 PRF (1/TPWMP) Main Channel SUB [kHz] 192 176.4 192 176.4 192 176.4 192 OUTPUT BITCLOCK FREQUENCY (1/TOBCLK) [MHz] 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 MINIMUM PULSE WIDTH (TPWMM) [ns] 122 133 122 133 122 133 122
Table 44 Output Bitclock Frequency Notes: 1. The correct Output Bitclock Frequency (TOBCLK) is generated by the built-in PLL of the WM8602 device. The incoming clock must meet the jitter specification defined in Table 3.
OUTPUT PHASE
The Phase control word determines whether the output of each channel is non-inverted or inverted. REGISTER ADDRESS R26 (1Ah) Output Phase BIT 6:0 LABEL PH[6:0] DEFAULT 0000000 Bit 0 1 6 Table 45 Phase DESCRIPTION Channel L R SUB Phase 1 = invert 1 = invert 1 = invert
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PWM OUTPUT CONFIGURATION
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The PWM output format can be defined with the PWMCFG setting defined in Table 46. REGISTER ADDRESS R27 (1Bh) PWM Output Configuration BIT 2:1 LABEL PWMCFG [1:0] DEFAULT 00 DESCRIPTION PWM Output State when output disabled or in standby mode: 01 = all PWM Outputs high 00 = all PWM Outputs low 10, 11 = high impedance PWM Output Phase 0 = PWM outputs in phase 1 = PWM outputs phase shifted to each other PWM Output Clock 0 = disabled 1 = enabled
3
PWMPH
1
7
PWMCLK
0
Table 46 PWM Output Configuration
OUTPUT CONFIGURATION
If required the WM8602 device can be disabled in a system by setting the TRI bit as defined in Table 47. Setting the TRI bit will set all output pins of the device to high impedance. REGISTER ADDRESS R28 (1Ch) Output Configuration BIT 0 TRI LABEL DEFAULT 0 DESCRIPTION Output Pins Mode 0 = Normal 1 = High Impedance
Table 47 Output Configuration
STANDBY, OUTPUT DISABLE AND RESET MODES
STANDBY
Setting the STDBY register bit selects a low power mode, and immediately configures the output to produce an output defined in Table 46 (PWMCFG). All trace of the previous input samples is removed, but all control register settings are preserved.
OUTPUT DISABLE (OPDIS) PIN AND REGISTER (OPDISR)
The OPDIS pin is provided to immediately shutdown the outputs, primarily for their protection. This is useful for short-circuit or thermal protection. The OPDIS pin can be configured in 2 modes: * * Synchronous Latched
In synchronous mode if OPDIS is high for longer than 100ns the outputs will be disabled. They will be enabled again at the end of a processing frame when OPDIS goes low for longer than 100ns. In latched mode if OPDIS is high for longer than 100ns, the outputs will be disabled and will remain off until OPDIS is reset via the control interface and the end of a processing frame is reached (Table 49). The output disable register (OPDISR) also allows the PWM outputs to be disabled via a register write. If OPDISR is set the PWM outputs will be disabled at the end of the next processing frame and enabled if OPDISR is reset at the end of the next processing frame.
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WM8602
REGISTER ADDRESS R29 (1Dh) Power Down 1 OPDISR 0 BIT 0 LABEL STDBY DEFAULT 1 DESCRIPTION Standby select: 0 : Normal Mode 1: Standby Mode Output disable register 0: Normal mode 1: PWM output disabled OPDIS Mode 0 : Synchronous 1: Latched, reset via Control I/F
2
MENA
1
Table 48 Power Down
EXTERNAL APPLICATION POWER-DOWN (EAPDB) PIN
The state of the output pin EAPDB shows whether the device is disabled (i.e. OPDIS input pin active or STDBY register set). EAPDB External Application Power Down STATE 1 0 (default) DESCRIPTION The device is operating correctly The outputs are disabled or the WM8602 device is in Standby (default) mode
Table 49 EAPDB Pin
RESET
The WM8602 device can be reset writing to the Reset register as defined in Table 50. REGISTER ADDRESS R30 (1Eh) Reset BIT 0 all LABEL RLENA RESET DEFAULT 0 0 DESCRIPTION Writing 1 to bit 0 of the register will reset OPDIS Writing all 1's to the register will reset the device and register settings
Table 50 Reset Note: RESET or RLENA will be applied at the end of the register write and released at the beginning of the next register write. I.e. to reset the OPDIS register write 1 to bit 0 of the Reset register and them write 0 to bit 0.
EXTERNAL POWER SUPPLY CLOCK
The WM8602 device can generate a clock signal for an external PSU (Power Supply Unit) which is available at the CLKPSU pin.
tHCLKPSU
CLKPSU tPCLKPSU
Figure 23 External Power Supply Clock
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REGISTER ADDRESS R31 (1Fh) PSU BIT 0 2:1 LABEL ENPSU CLKPSU[1:0] DEFAULT 0 00
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DESCRIPTION CLKPSU enable 1: enabled CLKPSU frequency 00: CLKPSU = fPRF 01: CLKPSU = fPRF/2 10: CLKPSU = fPRF/4 11: CLKPSU = fPRF/6 CLKPSU duty cycle 00: thclkpsu/tpclkpsu = 0.5 (50%) 01: thclkpsu/tpclkpsu = 0.125 (12.5%) 10: thclkpsu/tpclkpsu = 0.0625 (6.25%) 11: thclkpsu/tpclkpsu = 0.03125 (3.125%)
4:3
DCYPSU[1:0]
00
Table 51 PSU Clock Note: See Table 44 for specification of fPRF.
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WM8602
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. There are 30 registers with 9 bits per register. These can be controlled using the Control Interface.
REGISTER R0 (00h) R1 (01h) R2 (02h) R3 (03h) R4 (04h) R5 (05h) R10 (0Ah) R11 (0Bh) R12 (0Ch) R13 (0Dh) R14 (0Eh) R15 (0Fh) R16 (10h) R17 (11h) R18 (12h) R19(13h) R20 (14h) R21 (15h) R22 (16h) R23 (17h) R24 (18h) R25 (19h) R26 (1Ah) R27 (1Bh) R28 (1Ch) R29 (1Dh) R30 (1Eh) R31 (1Fh) R32 (20h) R33 (21h) ADDRESS 00_0000 00_0001 00_0010 00_0011 00_0100 00_0101 00_1010 00_1011 00_1100 00_1101 00_1110 00_1111 01_0000 01_0001 01_0010 01_0011 01_0100 01_0101 01_0110 01_0111 01_1000 01_1001 01_1010 01_1011 01_1100 01_1101 01_1110 01_1111 10_0000 10_0001 REMARKS Clocking Sample Rate Audio IF Format Input/Output Configuration Left Volume Right Volume Subwoofer Volume Dual Volume Control Mute Bass (1) Bass (2) EQ Band 1 Gain Control EQ Band 2 Gain Control EQ Band 3 Gain Control EQ Frequency Control Speaker Equaliser Deemphasis Peak Compressor F (1) Peak Compressor F (2) Peak Compressor SUB (1) Peak Compressor SUB (2) Zero Cross Output phase PWM Output Config Output Config Power Down Reset PSU Synchroniser (1) Synchroniser (2) BIT[8] 0 0 BCLKINV 0 UPDATE UPDATE UPDATE 0 0 0 0 0 0 0 0 0 0 0 FDEP 0 FDEP 0 0 0 0 0 0 0 0 0 0 0 PWMCLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOLD 0 0 0 0 0 0 DCYPSU GMAX 0 0 THRESH 0 0 0 0 0 0 1 1 1 0 0 0 0 THRESH 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 BIT[7] 0 0 MS 0 BIT[6] 0 0 LRSWAP 0 BIT[5] 0 0 0 0 BIT[4] 0 SRDET LRP 1 WL OPCFG 0 BIT[3] BIT[2] BIT[1] MPEG BIT[0] CMAST DEFAULT 0_0000_0011 0_0001_0000 FORMAT 0 1 0_0000_1010 0_0001_1001 0_1011_0001 0_1011_0001 0_1011_0001 0 1
LFEBOOST
PAGE REF 19 19 18 25 28 28 28 29 30 26 26 26 26 27 27 27 28 32 32 32 33 33 35 36 36 37 37 38 22 22
CLKDIV2 MEDGE SR
VOLFL (Left) Volume VOLFR (Right) Volume VOLS (Subwoofer) Volume 0
AMUTESB
0 1 0 LPENF
0 AMUTEF
DVCF SMUTE
0_0000_0000 0_0001_1110 0_0000_0001 0_0011_1111 0_1111_1111 0_1111_1111 0_1111_1111
0 1 1 1 1 EQ3CF 0 0 0 DCY 0 DCY ZCT
LPHPCO 1 HPENF
1 EQ1GF EQ2GF EQ3GF
1
EQ2CF LSEQ
1
EQ1CF LSCO
0_0011_1111 0_0000_1000
0 0
0 0
0 0 ATK
DEEMPH 0_0000_0000 PLENF 0_0000_0001 0_1101_1010
PLENSUB 0_0000_0001
0
0
0 ATK
0_1101_1010 ZCF 0_0001_1111 0_0000_0000
ZCSUB PH PWMPH 0 0 0
1
1
PWMCFG 0 MENA 0 CLKPSU GMIN SYNTO
0
0 TRI STDBY RLENA ENPSU
0_0000_1000 0_0000_0000 0_0000_0101 0_0000_0000 0_0000_0000
OPDISR 0
SYNCEN 0_0001_0101 0_0000_0100
Table 52 Register Map Description
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WM8602 DIGITAL FILTER CHARACTERISTICS
FILTER RESPONSES
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10 0 -10
Response (dB)
0.05 0.04 0.03
Response (dB)
-20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5
Frequency (Fs)
0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
2
2.5
3
0
0.1
0.2
Frequency (Fs)
0.3
0.4
0.5
Figure 24 Digital Filter Frequency Response - 32kHz
Figure 25 Digital Filter Ripple -32kHz
10 0 -10
Response (dB)
0.05 0.04 0.03
Response (dB)
-20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5
Frequency (Fs)
0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
2
2.5
3
0
0.1
0.2
Frequency (Fs)
0.3
0.4
0.5
Figure 26 Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 27 Digital Filter Ripple -44.1, 48 and 96kHz
10 0 -10
Response (dB)
0.05 0.04 0.03
Response (dB)
-20 -30 -40 -50 -60 -70 -80 0 0.2 0.4
Frequency (Fs)
0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
0.6
0.8
1
0
0.1
0.2
Frequency (Fs)
0.3
0.4
0.5
Figure 28 Digital Filter Frequency Response - 176.4kHz and 192kHz
Figure 29 Digital filter Ripple - 176.4kHz and 192kHz
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WM8602
DIGITAL DE-EMPHASIS CHARACTERISTICS
1
0
0
-2
Response (dB)
-4 -6 -8 -10 -12 0 2000 4000 6000 8000 10000 12000 14000 16000
Frequency (Hz)
Response (dB)
-1 -2 -3 -4 -5 -6 0 2000 4000 6000 8000 10000 12000 14000 16000
Frequency (Hz)
Figure 30 De-Emphasis Frequency Response (32kHz)
Figure 31 De-Emphasis Error (32kHz)
1
0
0
-2
Response (dB)
-4 -6 -8 -10 -12 0 5000 10000
Frequency (Hz)
Response (dB)
-1 -2 -3 -4 -5 -6
15000
20000
0
5000
10000
Frequency (Hz)
15000
20000
Figure 32 De-Emphasis Frequency Response (44.1kHz)
Figure 33 De-Emphasis Error (44.1kHz)
1 0 0 -2
Response (dB) Response (dB)
-1 -2 -3 -4 -5 -6
-4 -6 -8 -10 -12 0 5000 10000
Frequency (Hz)
15000
20000
0
5000
10000
Frequency (Hz)
15000
20000
Figure 34 De-Emphasis Frequency Response (48kHz)
Figure 35 De-Emphasis Error (48kHz)
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WM8602 APPLICATION NOTES
START-UP
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The WM8602 per default is switched off and the PWM output pins are static high, to protect any external circuit. When the device has been properly initialized and the output configuration has been defined then the device can safely be switched on. A typical start-up sequence is show in Figure 36.
Figure 36 WM8602 Start-up
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WM8602
POWER SUPPLY CONNECTIONS
The WM8602 has 3 individual power supplies. Figure 37 shows how these power supplies are connected and used on the chip and package.
Figure 37 WM8602 Power Supply Connections
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WM8602 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
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Figure 38 WM8602 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE Y1 C1, C2 C3 C4-C7 Table 53 External Components Description SUGGESTED VALUE 24.576 / 27.000MHz 22pF 4.7F 0.1F DESCRIPTION Crystal (15pF load, 500W) Capacitor NP0 0603 Capacitor Y5V 0805 Capacitor X7R 0603
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WM8602
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.D
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1 -C0.10 C
SEATING PLANE
L
0.25
L1
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 0.125 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8602 IMPORTANT NOTICE
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Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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